1. Field of the Invention
The present invention relates generally to semiconductors and, more particularly, to forming circuitry using wafer bonding.
2. Description of the Related Art
Advances in semiconductor manufacturing technology have provided computer chips with integrated circuits that include many millions of active and passive electronic devices, along with the interconnects to provide the desired circuit connections. As is well-known, most integrated circuits include laterally oriented active and passive electronic devices that are carried on a single major surface of a substrate. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. However, these laterally oriented devices generally operate slower than desired.
FIG. 1 shows a typical circuit 110 that includes a conventional p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 114 and a conventional n-channel MOSFET device 115. Devices 114 and/or 115 can be used in a convention memory circuit which includes known memory devices, such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). Devices 114 and 115 are carried by a p-type doped substrate 111 near its surface 111a. Device 114 is formed in an n-type doped well 116 formed in substrate 111 and includes a p+-type doped source 114a, a p+-type doped drain 114b, a dielectric region 114c, and a control terminal 114d. Dielectric region 114c is positioned on surface 111a and extends between source and drains 114a and 114b. Control terminal 114d is positioned on region 114c. Likewise, device 115 includes an n+-type doped source 115a, a n+-type doped drain 115b, a dielectric region 115c, and a control terminal 115d. Dielectric region 115c is positioned on surface 111a and extends between source and drains 115a and 115b. Control terminal 115d is positioned on region 115c. 
Devices 114 and 115 are typically called lateral or planar devices because their source and drains are positioned along a direction z oriented parallel to surface 111a. In operation, a p-type channel 114e and an n-type channel 115e are provided between source and drains 114a,114b and 115a,115b, respectively, in response to control signals provided to corresponding control terminals 114d and 115d. Hence, the current flow through channels 114e and 115e is substantially parallel to surface 111a. 
There are several problems with lateral devices, such as devices 114 and 115. One problem is that they operate slower than typically desired. FIG. 2 shows the doping concentration verses direction z shown in FIG. 1 for MOSFET 115. The p-type doping concentration in n-type channel 115e is constant between source 115a and drain 115b. Hence, the electric field between source 115a and drain 115b is practically zero without a signal being applied to drain 115b. As a result, the mobility of electrons through n-type channel 115e is less than it would be if there was a non-constant doping concentration in this region. As a consequence, MOSFET 115 operates slower because the doping concentration in n-type channel 115e is constant. The same is true for minority carries (i.e. holes) flowing through p-type channel 114e of MOSFET 114, however its doping concentration is not shown for simplicity.
Accordingly, it is highly desirable to provide new structures and methods for fabricating computer chips which operate faster.